The present disclosure relates generally to manufacture of integrated circuits (“ICs”) and, more particularly, to a system and method for partial air gap formation for providing interconnect isolation in such ICs.
As IC transistor densities increase, capacitive coupling between adjacent elements also increases. This increase in capacitive coupling further results in increased parasitic capacitance, which negatively impacts the speed and overall performance of the IC device.
Decreased resistance×capacitance (“R×C”) propagation delay is demanded in back-end-of-line (“BEOL”) interconnects due to resulting improvement in device performance. Introducing an air gap between interconnects is one manner by which the effective dielectric constant (“keff”) can be effectively reduced in such situations. Currently, there are several means by which an air gap may be introduced; however, each are costly and difficult to scale. In particular, they each require an additional sub-lithographic patterning step, an additional co-polymer patterning step, and/or non-conformal inter-metal layer deposition.